Regviz

Alif Semiconductor /AE512F80F5582AS_CM55_HE_View /ETH /ETH_DMA_CH0_CONTROL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as ETH_DMA_CH0_CONTROL

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Alif Semiconductor/AE512F80F5582AS_CM55_HE_View/ETH/ETH_DMA_CH0_CONTROL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0MSS0 (Val_0x0)PBLX8 0DSL

PBLX8=Val_0x0

Description

DMA Channel 0 Control Register

Fields

MSS

Maximum Segment Size This field specifies the maximum segment size that should be used while segmenting the packet. This field is valid only if the ETH_DMA_CH0_TX_CONTROL[TSE] bit is set. It is recommended to use a MSS value of 64 bytes or more.
PBLX8

8xPBL mode When this bit is set, the PBL value programmed in the ETH_DMA_CH0_TX_CONTROL[TXPBL] and ETH_DMA_CH0_RX_CONTROL[RXPBL] fields is multiplied by eight times. Therefore, the DMA transfers the data in 8, 16, 32, 64, 128, and 256 beats depending on the PBL value.

0 (Val_0x0): 8xPBL mode is disabled

1 (Val_0x1): 8xPBL mode is enabled
DSL

Descriptor Skip Length This bit specifies the Dword to skip between two unchained descriptors. The address skipping starts from the end of the current descriptor to the start of the next descriptor. When the DSL value is equal to zero, the DMA takes the descriptor table as contiguous.

Links

()

Register License

THIS SOFTWARE IS PROVIDED “AS IS”. NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. ALIF SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data